After a few days of construction - processor board part built (z80, buffers and clock generator) I've made a few changes.
I spotted a few mistakes on the memory chip select logic - still not sure I've got it quite right, when it boots the ROM bank at 3F000 (in the ROM) should be mapped at both 0000 and E000 in the Z80 address space. Any write to IO0-32 should then remap the ROM if bit 6 is set then RAM will be mapped at 0000....we'll see if this works.
Another change was to add 40106 to detect the reset and clock switches as normal TTL logic gave noise at the switch over (the 40106 is slow and has schmidtt inputs).
Lastly I moved the clock signal to be away from other lines and between two ground lines - it was giving a lot of cross-talk to other lines at 4MHz and as this is the highest frequency line I supposed it would be better away from the other lines. If the other lines prove to cross-talk too much I may have to completely re-think the bus!
Anyway here's the schematics so far....