Tuesday, 11 August 2009

Improved memory logic

After a bit of a redesign I've now got both CMOS and NMOS working at 4MHz reliably. It turns out that the memory board logic had too long a propagation to the ROM and RAM0 lines - caused by having two cascade '138s and lots of '02s and '04s in the way.

After a bit of head scratching I've now got the control logic down to the attached diagram and this seems to be a lot more reliable at speed and leaves a nice WINDOW signal which will be used as the window for the graphics memory when I get round to trying out the VGA card.


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